Integrated circuit design generally comprises two major steps: placement and routing. During the placement step, the positions and orientations of cells and blocks are determined. During the routing step, interconnects or wires are added to connect ports on the placed cells and blocks. Integrated circuit design data is typically partitioned and organized in a design hierarchy. During placement and routing, a design tool may flatten the hierarchy in its internal data structure such that the design is effectively treated as having only two levels in its hierarchy. In such cases, the top level of the design comprises leaf cells, and placement and routing are performed on the leaf cells. Alternatively, in another approach for placement and routing, the design hierarchy may not be internally flattened. Instead, blocks in the design hierarchy are placed and routed individually, with upper level blocks not placed and routed until placement and routing is complete for lower level blocks. In such cases, unconstrained consumption of routing resources during the routing of lower level blocks may result in difficulties in generating a good routing plan for upper level blocks.